CSRC=SLAVE_MODE, SSSDIS=SEND, FES=RISING, TSBYPASS=SYNCHRONIZED, CCCLR=SOFTWARE, CSCEN=ON_CHARACTER, SYNC=DISABLED
Synchronous mode control register.
| SYNC | Enables synchronous mode. 0 (DISABLED): Disabled. 1 (ENABLED): Enabled. |
| CSRC | Clock source select. 0 (SLAVE_MODE): Slave mode. Synchronous slave mode (SCLK in) 1 (MASTER_MODE): Master mode. Synchronous master mode (SCLK out) |
| FES | Edge sampling. 0 (RISING): Rising. RxD is sampled on the rising edge of SCLK. 1 (FALLING): Falling. RxD is sampled on the falling edge of SCLK. |
| TSBYPASS | Transmit synchronization bypass in synchronous slave mode. 0 (SYNCHRONIZED): Synchronized. The input clock is synchronized prior to being used in clock edge detection logic. 1 (NOT_SYNCHRONIZED): Not synchronized. The input clock is not synchronized prior to being used in clock edge detection logic. This allows for a high er input clock rate at the expense of potential metastability. |
| CSCEN | Continuous master clock enable (used only when CSRC is 1) 0 (ON_CHARACTER): On character. SCLK cycles only when characters are being sent on TxD. 1 (CONTINUOUSLY): Continuously. SCLK runs continuously (characters can be received on RxD independently from transmission on TxD). |
| SSSDIS | Start/stop bits 0 (SEND): Send. Send start and stop bits as in other modes. 1 (DO_NOT_SEND): Do not send. Do not send start/stop bits. |
| CCCLR | Continuous clock clear 0 (SOFTWARE): Software. CSCEN is under software control. 1 (HARDWARE): Hardware. Hardware clears CSCEN after each character is received. |
| RESERVED | Reserved. The value read from a reserved bit is not defined. |